1. Field of the Invention
The present invention relates to a method for manufacturing a stacked capacitor which can be used in a memory cell of a dynamic random access memory (DRAM).
2. Description of the Related Art
Generally, in a DRAM, each memory cell is formed by one metal oxide semiconductor (MOS) transistor and one capacitor. Also, recently, a stacked capacitor, which has two electrode layers with an insulating layer therebetween, has been used as such a capacitor, to thereby increase the density of the DRAM.
According to a prior art method for manufacturing a stacked capacitor, an insulating layer is deposited on a semiconductor substrate including a drain region of a MOS cell transistor, and is patterned by a photolithography process to create a contact hole leading to the drain region. Then, a conductive layer, i.e., a lower electrode layer is deposited and is connected to the drain region. Finally, an insulating layer and a conductive layer, i.e., an upper electrode layer, are deposited to thereby obtain a stacked capacitor.
In the above-mentioned prior art stacked capacitor manufacturing method, however, since the contact hole for the capacitor lower electrode is formed directly by the photolithography process, so that the size of the contact hole is dependent upon the photolithography process, it is impossible to make the size of the contact hoe smaller than a size determined by the photolithography process. Therefore, there is a limit to the integration density of the stacked capacitor in accordance with the photolithographyprocess.